1. Field of the Invention
The present invention relates to a semiconductor device having a chip-on-chip (COC) structure wherein first and second semiconductor chips are adhered to each other in a form so that the surfaces thereof are opposed to each other.
2. Description of the Prior Art
An increase in the performance and functionality of a variety of electronic appliances can be implemented by increasing the performance and functionality of semiconductor devices which are core parts of such electronic appliances. Development of a system-on-chip (SOC) wherein a variety of functional blocks each having a desired function are mounted on a single chip, and at the same time development of a system-in-package (SIP) wherein a plurality of chips is mounted in a three-dimensional form and contained in a package have been making rapid progress recently. In particular, the SIP having a chip-on-chip (COC) structure, have recently attracted special attention due to the possibility for reduction of the mounting area thereof, in comparison with SOC wherein two functional blocks are formed on a single chip; and due the possibility of creating an increase in speed which is equal to or greater than that of SOC.
FIG. 6 is a chip configuration diagram showing an example of a system-on-chip according to a prior art. In this diagram a system-on-chip on which a plurality of functional blocks is mounted is denoted as 11, a memory macro mounted on system-on-chip 11 is denoted as 12, a memory macro control circuit mounted on system-on-chip 11 is denoted as 13, a group of internal signal connection lines for connecting memory macro 12 to memory macro control circuit 13 is denoted as 14, an external connection terminal is denoted as 15, and a group of external signal connection lines for connecting memory macro 12 to external connection terminals 15 is denoted as 16.
The operation of the conventional system-on-chip configured as described above is below described. At the time when the system-on-chip is in a conventional operational mode memory macro 12 operates under the control of memory macro control circuit 13 via group 14 of internal signal connection lines; while at the time when the system-on-chip is in a memory macro test mode, memory macro 12 is tested by an external control signal that is inputted from an external connection terminal 15 via group 16 of external signal connection lines.
The above described conventional semiconductor device, having a system-on-chip structure wherein a plurality of functional blocks that includes a memory macro is mounted on a single chip is considered to be a good product as a semiconductor chip, only in the case wherein all of the functional blocks that have been mounted operate correctly, however, a problem arises wherein the semiconductor chip is regarded as defective in the case wherein any one of the functional blocks that have been mounted is defective and does not operate correctly, even when the majority of functional blocks operate correctly. This problem becomes more significant as the capacity of memory macro that is mounted on the chip is increased, leading to an increase in the area of the chip itself, thus making it difficult to increase the production yield.
As a measure for avoiding such a problem, mounting of a memory macro in one chip together with other functional blocks has been reviewed; and semiconductor devices having a COC structure that is formed of two chips, a memory macro chip and a chip having other functions, have attracted attention in recent years; however the following problem arises in the case wherein a memory macro which has been mounted on a conventional system-on-chip is formed in a separate chip for COC connection.
A memory macro that is mounted on a conventional system-on-chip is, in general, characterized in having a configuration of multiple-bit input/output, and in that the memory macro has a very great number of connection terminals in total, including a great number of internal signal connection terminals for the normal operation mode, and a great number of external signal connection terminals for the memory macro test mode. Therefore a problem arises in the case wherein the above described memory macro is formed in a separate chip for COC connection without changing the specifications thereof, because of the great number of inter-chip connection terminals, which leads to an increase in the areas of the chips and to a reduction in the yield of the product, resulting from defects in the connection between the chips. Here, only the chip on which a memory macro control circuit having a great chip area is mounted, can directly be controlled from the outside after the connection of the chips in the case wherein the memory macro is formed in a separate chip for COC connection without changing the specification thereof wherein the area of the chip on which the memory macro control circuit is mounted, for example, is assumed to be great, while the area of the chip on which the memory macro is mounted is assumed to be small, and therefore the number of inter-chip connection terminals becomes significantly great in order to make it possible for the test of the memory macro itself to be carried out after the connection of the chips, because the terminals for the memory macro test mode are also required to be connected to the terminals of the chips on which the memory macro control circuit is mounted.